From 660a66b128fd9e9256ccfd90a0380e09b3484c01 Mon Sep 17 00:00:00 2001
From: Joy Cho <joy.cho@hardkernel.com>
Date: Tue, 27 Mar 2018 16:20:15 +0900
Subject: [PATCH] drm: exynos: Add a pixel clock to support Vu7A+

To support Vu7A+, a pixel clock, 49MHz is needed.
But there is no exact hdmi phy table of exynos5422,
so the closest table of 50.04MHz will be used
as a workaround.

- Vu7A+ timing
Detailed mode (1) : Clock 49 MHz, 255 mm x 255 mm
               1024 1029 1042 1312 hborder 0
                600  602  605  622 vborder 0
               -hsync +vsync

- 1024x600p60hz timing
Detailed mode: Clock 50.400 MHz, 355 mm x 208 mm
               1024 1048 1184 1344 hborder 0
                600  601  604  625 vborder 0
               -hsync +vsync

Change-Id: I88d1739649341c5312d6516ffc2ee33a129c6f89
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index b0687f17a9c07..ab9bfbd133416 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -463,6 +463,20 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = {
 			0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 		},
 	},
+	/*
+	 * To support Vu7A+, pixel clock 49MHz is needed
+	 * but we don't have the exact HDMI PHY table
+	 * so as a workaround, the closest table will be used.
+	 */
+	{
+		.pixel_clock = 49000000,
+		.conf = {
+			0x01, 0x51, 0x2A, 0x32, 0x42, 0x30, 0x00, 0xC4,
+			0x83, 0xE8, 0xFC, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
+			0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86,
+			0x54, 0x7A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
+		},
+	},
 	{
 		.pixel_clock = 50400000,
 		.conf = {
